Semiconductor integrated circuit (IC) technology has experienced rapid progress including the continued minimization of feature sizes and the maximization of packing density. The minimization of feature size relies on improvement in photolithography and its ability to print smaller features or critical dimensions (CD). This is further related to wafer alignment. The wafer alignment is performed in the lithography scanner. The scanner will expose the wafer based on the alignment result. To reduce the overlay error, it is needed to improve the alignment accuracy and the overlay measurement accuracy result. However, during a photolithography process, the wafer may experience wafer bending and deformation caused by wafer clamping (chucking) and other factors, such as thermal treatment. The existing alignment method does not consider the positioning error caused by the wafer clamping. The positioning error measured is different from that experienced by the lithography scanner. Furthermore, the existing alignment measurement is inaccurate and inefficient.
Therefore, an apparatus for lithography patterning and a method utilizing the same are needed to address the above issues associated with the alignment.